PLL (1 phase)

Block appearance in REPEAT VISION

 Block PLL (1 phase) implements the phase frequency autotuning loop (PLL) receiving a single-phase input signal.

 The block is based on the standard structure of the single-phase PLL[1], its block diagram is given in Fig. 1.

Fig. 1 Block diagram of single-phase PLL

Note

This model is designed to calculate the frequency and phase of the input sinusoidal signal

 Model consists of the following functional parts:

1. Phase detector. Generates phase difference signal of input sinusoid and phase generator. Also, the block implements the possibility of filtering the phase difference signal using the Moving Average Filter (MAF). It can be activated via Moving average

Important

A signal in relative units is expected at the input.

Note

In the block, it is possible to implement automatic transfer of the signal from named units to relative ones by multiplying by a coefficient calculated from the input signal module. To enable such functionality, the block provides the property Adaptive gain.

2. Filter. It is a PID controller that generates a signal based on the phase difference determined by the phase detector. In fact, this signal is the frequency of the input sinusoid in \(\frac{rad}{s}\). In this case, the initial value of this frequency is set in the Initial frequency. The block diagram of this controller implementation in the block is given in Fig. 2.

Fig. 2 The block diagram of PID controller implementation

Note

In the PID controller design, a low-pass filter described by a first-order transfer function is implemented in the differential channel. The filter time constant is specified in the ‘Derivative filter time constant`.

3. Phase generator (sawtoothlike). It is an integrator that resets when the phase reaches a value of \(2\cdot\pi\) and thus forms a sawtoothlike signal at the output. Control signal from PID controller is transmitted to input of this unit.

  The input frequency is determined from the PID controller output signal. In its simplest form, it is determined by transferring this signal from \(\frac{rad}{s}\) to Hz. The block implements the ability to enable the limitation of the rate of change of the signal, as well as its filtering after limitation. Use ROCOF limiter and Frequency filter properties to enable this functionality.

1.  Properties

Property	Default Value	Description	Units of measurement
Minimum frequency, available if Adaptive gain-On or Moving average-On	45.0	-	Hz
Initial phase	0.0	-	deg
Initial frequency	60.0	-	Hz
Proportional gain	180.0	-	-
Integral gain	3200.0	-	-
Derivative gain	1.0	-	-
Derivative filter time constant	0.01	-	s
Frequency filter cut-off frequency, available when Moving average-On	100.0	-	Hz
ROCOF limit, available when ROCOF limiter-On	1000.0	-	-
Adaptive gain	On	-	-
Moving average	On	-	-
Frequency filter	On	-	-
ROCOF limiter	On	-	-
Sampling type: Fundamental project frequency decimation; Sample time; Sampling frequency	Fundamental project frequency decimation	-	-
Sample time, available when selecting Sampling type-Sample time	0.05	-	s
Decimation factor of project fundamental discretization frequency, available when selecting Sampling type-Fundamental project frequency decimation	1	-	-
Sampling frequency, available when selecting Sampling type-Sampling frequency	20.0	-	Hz

2.  Inputs and outputs

Parameters	Input/Output	Description	Units of measurement	Port type
Input signal	Input	-	-	Automation
Frequency	Output	-	Hz	Automation
Angle	Output	-	rad	Automation

In order to see the connection capabilities of the block, you need to go to page Description of block ports

3.  Sources

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[1]

Karimi-Ghartemani, M. Enhanced phase-locked loop structures for power and energy applications / M. Karimi-Ghartemani. - IEEE Press Series on Microelectronic Systems, 2014. – 216 p.